LXP-LB series hybrid inverter (LXP-LB-EU 8-10K) Modbus register map

Notes

Source: Shenzhen Lux Power Technology "Modbus RTU Protocol" (administrator edition, 2025/6/13; version history V00 2024.02.23 to V23 20250614) - the vendor's own document, http://www.luxpowertek.com, read from the public mirror https://github.com/OwlBawl/luxpower-ha-modbus/blob/main/ModBus_protocol_updated_on_2025.06.14.pdf (luxpowertek.com did not expose the PDF in its own document index). Section 2 fixes the interface: RS-485, 19200 bps, one start bit, 8 data bits, no parity, one stop bit, minimum polling period 1 s, and a reversed byte order - 0x01 0x02 reads as 0x0201 and 0x01 0x02 0x03 0x04 as 0x04030201 - hence byte order LittleEndian and word order LowFirst. The document numbers the input registers from 0 and says a full 40-register request must start at 0, 40, 80, ..., which is the vendor's own statement that these are wire addresses; they are stored unchanged (zero based). The vendor does not state a factory slave address. The unit 1 recorded here is a placeholder, not a cited value, and the user must set the inverter's own address on site. Deliberate omissions: the settings (holding-register) block, because in this revision its rows pack several settings into one register's bit ranges and the bit-to-value mapping is printed as a separate model file; the power-factor register (19), which is not a plain scale but folds above 1000 ((1000-x)/1000) and cannot be expressed as a fixed factor; the SOH row, which is printed under SOC without a register number of its own; the US-model L1N/L2N block (193-204) and the PV4-PV6 block (217-231), which belong to other model variants; and the BMS mirror block (80-113), which duplicates values the BMS itself serves.